The present invention relates to a manufacturing technology for semiconductor devices, and in particular relates to a technology effective in improving the reliability in an electric inspection which is performed when a semiconductor device is being mounted on a socket.
Japanese Patent Laid-Open No. 2007-163463 (Patent Document 1) discloses a structure, in which in the inspection of a semiconductor integrated circuit, an external electrode on a first side of the semiconductor integrated circuit is electrically connected to an inspection wiring substrate via a first conductive contact while an external electrode on a second side of the semiconductor integrated circuit is electrically connected to the inspection wiring substrate via a second conductive contact, a wiring substrate, and a third conductive contact; and a technique for inspection by using this structure.
Moreover, Japanese Patent Laid-Open No. 2009-20105 (Patent Document 2) discloses a technique for simultaneously inspecting a connection state of a connection terminal provided on the lower surface of an object to be inspected and a connection state of a connection terminal provided on the upper surface.